Delta modulation

A delta modulation (DM or Δ-modulation) is an analog-to-digital and digital-to-analog signal conversion technique used for transmission of voice information where quality is not of primary importance. DM is the simplest form of differential pulse-code modulation (DPCM) where the difference between successive samples is encoded into n-bit data streams. In delta modulation, the transmitted data are reduced to a 1-bit data stream representing either up (↗) or down (↘). Its main features are:

The analog signal is approximated with a series of segments.
Each segment of the approximated signal is compared to the preceding bits and the successive bits are determined by this comparison.
Only the change of information is sent, that is, only an increase or decrease of the signal amplitude from the previous sample is sent whereas a no-change condition causes the modulated signal to remain at the same ↗ or ↘ state of the previous sample.

To achieve high signal-to-noise ratio, delta modula

An All-Digital 1.25 Mbps 5-Subcarrier OFDM Backscatter Uplink with Delta-Sigma Modulation for Improved Spurious-Free Dynamic Range

James Daniel Rosenthal

This paper describes an all-digital backscatter modulation approach leveraging delta-sigma modulation (DSM) to improve the in-channel spectral characteristics of orthogonal frequency division multiplexed (OFDM) backscatter communication. We demonstrate through numerical simulations and experimental validation that DSM can improve the spurious-free dynamic range (SFDR) of OFDM subcarriers generated by a low-resolution impedance digital-to-analog converter (DAC), such as an RF switch having two or four different impedance states. We present the design and validation of a prototype OFDM backscatter uplink with DSM implemented with all-digital logic in an FPGA. A single-pole-four-throw CMOS RF switch (i.e. 2-bits of impedance DAC resolution) serves as the backscatter modulator. We experimentally validated the DSM approach with a 2.4 GHz, five-subcarrier OFDM backscatter uplink and a four-times oversampling DSM at up to 1.25 Mbps. In this scenario, the DSM improved the SFDR by 43 dB within the subcarrier band while reducing the overall noise floor in the same band by 11.3 dB. These results confirm that a DSM approach can be used to control quantization noise and improve the spectral characteristics of low-resolution digital impedance modulators for backscatter communication in scenarios where in-channel SFDR is more important than wideband noise performance.

IEEE2022

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

A novel frequency synthesizer with a strong emphasis on low-power consumption (2mW) was developed for this thesis. A BAW-resonator was used for the design of the high-frequency oscillator. The BAW's high Q-Factor ensured a minimal power consumption, while providing outstanding phase noise performance. This type of frequency synthesizer can be implemented in practically every mobile wireless system standard, which is relying on batteries as the power supply, such as Bluetooth, Zigbee and others. For this work, a Bluetooth-compatible standard was taken in order to derive the system specifications. The frequency synthesizer then was designed and implemented in a 180nm CMOS process. The approach of the "Sliding-IF" architecture was chosen and modified in order to take full advantage on the BAW oscillator. Therefore a two-stage frequency translation of the signal was necessary, similar to the super-heterodyne transceiver topology. The channel selection and the frequency error correction is done at the second stage, since the BAW-based oscillator does practically not provide any frequency tuning. For this, a Delta-Sigma-Modulator based Fractional-N PLL was developed. A system supply voltage of 1.2V was chosen in order to keep power consumption as low as possible. This supply voltage can also be easily supplied by AA or AAA-batteries and a low-voltage regulator. The most important technique to reduce overall power consumption was to reduce the high-frequency requirements to the system blocks. This was done by modifying the "Sliding-IF" architecture and by the use of the BAW resonator. The minimization of the power consumption required careful choice and design of each of the system blocks. For this, several approaches were analyzed, especially the topology of each block and its optimization were important. A special emphasis on the analysis, design and discussion was also made on the noise, and especially the phase noise. A ring oscillator, a LC-VCO and a BAW-oscillator were implemented and measured in order to validate the theory and the simulation results. The complete frequency synthesizer with an Automatic Amplitude Control, Frequency Dividers, Mixer, Charge-Pump, Phase-Frequency Detector and a Delta-Sigma-Modulator was designed and implemented. This thesis was elaborated in the frame of the MiNAMI and MiMOSA projects of the European research programme (FP6).

EPFL2009

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

EPFL2009

Integrated sigma-delta interface for capacitive sensors

An All-Digital 1.25 Mbps 5-Subcarrier OFDM Backscatter Uplink with Delta-Sigma Modulation for Improved Spurious-Free Dynamic Range

Low power frequency synthesizer for mobile communications systems

Integrated sigma-delta interface for capacitive sensors

Low power frequency synthesizer for mobile communications systems

An All-Digital 1.25 Mbps 5-Subcarrier OFDM Backscatter Uplink with Delta-Sigma Modulation for Improved Spurious-Free Dynamic Range