Concept

Branch predictor

Related publications (100)

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Dynamic feature selection for hardware prediction

Babak Falsafi

Most hardware predictors are table based (e.g. two-level branch predictors) and have exponential size growth in the number of input bits or features (e.g. previous branch outcomes). This growth severely limits the amount of predictive information that such ...

2006

Simulation sampling with live-points

Babak Falsafi

Current simulation-sampling techniques construct accurate model state for each measurement by continuously warming large microarchitectural structures (e.g., caches and the branch predictor) while functionally simulating the billions of instructions betwee ...

2006

Statistical sampling of microarchitecture simulation

Babak Falsafi

Current software-based micro architecture simulators are many orders of magnitude slower than the hardware they simulate. Hence, most microarchitecture design studies draw their conclusions from drastically truncated benchmark simulations that are often in ...

2006

Improving instruction cache performance in OLTP

Anastasia Ailamaki

Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...

Association for Computing Machinery2006

A Predictable Communication Scheme for Embedded Multiprocessor Systems

Paolo Ienne, Mehmet Harmanci, Yusuf Leblebici

Networks-on-Chip are emerging as a widely accepted alternative for the traditional bus architectures. However, their applicability by the system designers is far away from being intuitive due to their lack of predictability. This communication predictabili ...

2006

A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control

Giovanni De Micheli, Srinivasan Murali

When designing a System-on-Chip (SoC) using a Network-on- Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power consumption is due to the buffers in the Network Interfaces (NIs) needed to ...

2006

TurboSMARTS: Accurate microarchitecture simulation sampling in minutes

Babak Falsafi

Recent research proposes accelerating processor microarchitecture simulation through statistical sampling. Prior simulation sampling approaches construct accurate model state for each measurement by continuously warming large microarchitectural structures ...

2005

Dynamically Trading Frequency for Complexity in a GALS Microprocessor

Microprocessors are traditionally designed to provide “best overall” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques that save energy by “downsizing” hardware resources that are u ...

2004

Efficient resource sharing in concurrent error detecting superscalar microarchitectures

Babak Falsafi

Previous proposals for soft-error tolerance have called for redundantly executing a program as two concurrent threads on a superscalar microarchitecture. In a balanced superscalar design, the extra workload from redundant execution induces a severe perform ...

2004

Accurate and complexity-effective spatial pattern prediction

Babak Falsafi

Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixed cache line sizes to balance the exploitation of spatial and temporal locality, a ...

2004