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We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down t ...
We present a new scalable architecture for the realization of fully programmable rank order filters (ROF). Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in th ...
A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arran ...
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down t ...
There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of ...
We report fast modulation (>30 GHz) in a SOI resonant cavity using integrated Bragg mirrors and a gate-all-around transistor as active element. Modulation depth >90% can be obtained in 12.5 μm long devices. ...
Data storage cells are formed on a substrate (13). Each of the data storage cells includes a field effect transistor with a source (18), drain (22) and gate (28) and a body arranged between the source and drain for storing electrical charge generated in th ...
This paper describes some techniques to improve the output waveform quality of multilevel inverts fed-indction machines. The investigated topologies are the diode-clamped and series-connection of H-bridges. Thesetechinques are based on an unequal dc-voltag ...
This paper presents a micropower second-order low-pass filter using the log-domain principle and integrated in a 0.35-μm CMOS process. It has been designed as an antialiasing filter for a DECT transceiver with a 45-kHz nominal cutoff frequency. The circuit ...
Data storage cells are formed on a substrate (13). Each of the data storage cells includes a field effect transistor with a source (18), drain (22) and gate (28) and a body arranged between the source and drain for storing electrical charge generated in th ...