Concept
Prefetch input queue
Related publications (12)
HPCache: memory-efficient OLAP through proportional caching revisited
Anastasia Ailamaki, Periklis Chrysogelos, Hamish Mcniece Hill Nicholson
Analytical engines rely on in-memory data caching to avoid storage accesses and provide timely responses by keeping the most frequently accessed data in memory. Purely frequency- and time-based caching decisions, however, are a proxy of the expected query ...
New York2023HPCache: Memory-Efficient OLAP Through Proportional Caching
Anastasia Ailamaki, Periklis Chrysogelos, Hamish Mcniece Hill Nicholson
Analytical engines rely on in-memory caching to avoid disk accesses and provide timely responses by keeping the most frequently accessed data in memory. Purely frequency- & time-based caching decisions, however, are a proxy of the expected query execution ...
ACM2022RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs
Babak Falsafi, Alexandros Daglis, Mark Johnathon Sutherland
Modern online services come with stringent quality requirements in terms of response time tail latency. Because of their decomposition into fine-grained communicating software layers, a single user request fans out into a plethora of short, μs-scale RPCs, ...
ACM2019Memory Systems and Interconnects for Scale-Out Servers
The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...
EPFL2015Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs
Marco Mattavelli, Endri Bezati, Ab Al Hadi Bin Ab Rahman, Anatoly Prihozhy
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-level system design. The pipeline synthesis is applied to dataflow programs whose operators are translated into graphs and dependencies relations that are th ...
Ieee-Inst Electrical Electronics Engineers Inc2015A Primer on Hardware Prefetching
Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution r ...
Morgan & Claypool2014Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis
According to the World Health Organization, lifestyle-related diseases, e.g., cardiovascular diseases are the major cause of mortality worldwide. An accurate and continuous medical supervision is highly required for diagnosis and treatment of such diseases ...
EPFL2013NOC-Out: Microarchitecting a Scale-Out Processor
Babak Falsafi, Boris Robert Grot, Pejman Lotfi Kamran
Scale-out server workloads benefit from many-core processor organizations that enable high throughput thanks to abundant request-level parallelism. A key characteristic of these workloads is the large instruction footprint that exceeds the capacity of priv ...
2012Temporal instruction fetch streaming
Anastasia Ailamaki, Babak Falsafi, Michael Ferdman
L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the application, library, and OS instruction working sets of these wo ...
2008Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microarchitecture
Applications vary in the degree of instruction level parallelism (ILP) available to be exploited by a superscalar processor. The ILP can also vary significantly within an application. On one end of the microarchitecture space are monolithic superscalar des ...
2004