Concept

Processor register

Related publications (110)

Energy-Aware Compilation and Hardware Design for VLIW Embedded Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Tomorrow's embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. In this context, the register file is a key source of power consumption and its inappropriate design and management ...

2007

STMBench7: A Benchmark for Software Transactional Memory

Rachid Guerraoui, Michal Kapalka

Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse-grained locking and easier to use than fine-grained locking. However, STM im ...

2007

Amnesic Distributed Storage

Rachid Guerraoui

Distributed storage algorithms implement the abstraction of a shared register over distributed base objects. We study a specific class of storage algorithms, which we call amnesic: these have the pragmatic property that old values written in the implemente ...

2007

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable be ...

2007

An Application-Specific Design Methodology for On-chip Crossbar Generation

Giovanni De Micheli, Luca Benini, Srinivasan Murali

Designing a power-efficient interconnection architec- ture for MultiProcessor Systems-on-Chips (MPSoCs) satisfying the application performance constraints is a nontrivial task. In order to meet the tight time-to-market constraints and to effec- tively hand ...

Institute of Electrical and Electronics Engineers2007

PAI: A lightweight mechanism for single-node memory recovery in DSM servers

Babak Falsafi

Several recent studies identify the memory system as the most frequent source of hardware failures in commercial servers. Techniques to protect the memory system from failures must continue to service memory requests, despite hardware failures. Furthermore ...

2007

Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is to allocate the minimum number of registers such that no scalar variable is sp ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2007

Low Overhead DFT Using CDFG by Modifying Controller

Pejman Lotfi Kamran

A novel design-for-test (DFT) method that requires minor modifications to the controller in the register-transfer level (RTL) description of a circuit is presented. The control/data flow graph representation of an RTL circuit is used for analysing the test ...

2007

Compiler-Driven Leakage Energy Reduction in Banked Register Files

Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo

Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption ...

2006

Compilation for Delay Impact Minimization in VLIW Embedded Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Tomorrow’s embedded devices need to run high resolution multimedia as well as need to support multistandard wireless systems which require an enormous computational complexity with a very low energy consumption and very high performance constraints. In thi ...

IEEE Press2006

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