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The paper discusses implementations of fine-grain memory access control, which selectively restricts reads and writes to cache-block-sized memory regions. Fine-grain access control forms the basis of efficient cache- coherent shared memory. The paper focus ...
A global approach to the problem of model-based control of fast parallel robots is proposed in this work. Fundamental differences between the well-known serial arms and parallel manipulators are first explained. A formalism inspired from Denavit-Hartenberg ...
The article analyses the behavior of two kinds of multiprocessor multidisk storage server architectures for a data intensive application, namely for spatial queries in geographical information systems (GIS). The two kinds of servers are: (1) a workstation ...
We introduce a new organization for multi-bank caches: the skewed-associative cache. A two-way skewed-associative cache has the same hardware complexity as a two-way set-associative cache, yet simulations show that it typically exhibits the same hit ratio ...
Message passing and shared memory are two techniques parallel programs use for coordination and communication. This paper studies the strengths and weaknesses of these two mechanisms by comparing equivalent, well-written message-passing and shared-memory p ...
A network multicomputer is a multiprocessor in which the processors are connected by general-purpose networking technology, in contrast to current distributed memory multiprocessors where a dedicated special-purpose interconnect is used. The advent of high ...
We describe a parallel implementation of a genetic linkage analysis program that achieves good speedups, even for analyses on a single pedigree and with a single starting recombination fraction vector. Our parallel implementation has been run on three diff ...
We believe the paucity of massively parallel, shared-memory machines follows from the lack of a shared-memory programming performance model that can inform programmers of the cost of operations (so they can avoid expensive ones) and can tell hardware desig ...
We introduce a new organization for multi-bank caches: the skewed-associative cache. A two-way skewed-associative cache has the same hardware complexity as a two-way set-associative cache, yet simulations show that it typically exhibits the same hit ratio ...
A scalable multiprocessor raster image processor that generates printed circuit plots in alternating band buffers is described. Synchronous raster plotting systems and the development of mask creation for producing printed circuits are reviewed. The genera ...