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OpenCores is a community developing digital open-source hardware through electronic design automation (EDA), with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and significantly reduce development costs. A number of companies have been reported as adopting OpenCores IP in chips, or as adjuncts to EDA tools. OpenCores is also sometimes cited as an example of open source in the electronics hardware community. OpenCores has always been a commercially owned organization. In 2015, its core active users established the independent Free and Open Source Silicon Foundation (FOSSi Foundation), and created another directory on the librecores.org website as the basis for all future development, independent of commercial control. It has been shut down to redirect to a post on the FOSSi Foundation website seven years later in favor of a simple web search, reasoning that "free and open source silicon is no longer a dream". Damjan Lampret, one of the founders of OpenCores, stated on his website that it began in 1999. The new website and its objectives were reported publicly by EE Times in 2000 and CNET News in 2001. Through the following years it was supported by advertising and sponsorship, including by Flextronics. In mid-2007 an appeal was put out for a new backer. That November, Swedish design house ORSoC AB agreed to take over maintenance of the OpenCores website. EE Times reported in late 2008 that OpenCores had passed the 20,000 subscriber mark. In October 2010 it reached 95,000 registered users and had approximately 800 projects. In July 2012 it reached 150,000 registered users. During 2015, ORSoC AB formed a joint venture with KNCMiner AB to develop bitcoin mining machines. As this became the primary focus of the business, they were able to spend less time with the opencores.org project. In response to the growing lack of commitment, the core OpenRISC development team set up the Free and Open Source Silicon Foundation (FOSSi), and registered the librecores.

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Open-source hardware

Open-source hardware (OSH) consists of physical artifacts of technology designed and offered by the open-design movement. Both free and open-source software (FOSS) and open-source hardware are created by this open-source culture movement and apply a like concept to a variety of components. It is sometimes, thus, referred to as FOSH (free and open-source hardware). The term usually means that information about the hardware is easily discerned so that others can make it – coupling it closely to the maker movement.

Semiconductor intellectual property core

In electronic design, a semiconductor intellectual property core (SIP core), IP core, or IP block is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores can be licensed to another party or owned and used by a single party. The term comes from the licensing of the patent or source code copyright that exists in the design. Designers of system on chip (SoC), application-specific integrated circuits (ASIC) and systems of field-programmable gate array (FPGA) logic can use IP cores as building blocks.

Soft microprocessor

A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic (e.g., ASIC, FPGA, CPLD), including both high-end and commodity variations. Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit.

Advancing atomic force microscopy through open source instrumentation

Mustafa Kangül

Atomic force microscopy (AFM), a member of the scanning probe microscopy (SPM) family, holds a unique position as a nano-characterization instrument in the fields of physics, chemistry, and biology. Its ability to provide atomic resolution and operate in v ...

EPFL2023

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

Edoardo Charbon, Francesco Regazzoni

This work proposes the first fine-grained configurable cell array specifically tailored for the implementation of cryptographic algorithms that can be configured using widely adopted hardware description languages. Our solution can be added as a small, cry ...

IEEE2018

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Shashi Kanth Bobba, Subhasish Mitra

The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of Carb ...

Assoc Computing Machinery2014

IcySoC: Inexact Sub- and Near-Threshold Systems

Covers inexact sub- and near-threshold systems for ultra-low power devices and multi-scale systems engineering.

Generating a CLK Generator (PLL) IP in Vivado EE-334: Digital systems design

Covers the process of generating a Clock Generator (PLL) IP in Vivado using the Clocking Wizard tool.

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