Publications related to Pentium

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function e(x)

Felix Schürmann, Francesco Cremonesi, Timothée Ewart

The evaluation of small degree polynomials is critical for the computation of elementary functions. It has been extensively studied and is well documented. In this article, we evaluate existing methods for polynomial evaluation on superscalar architecture. ...

2020

Real-Time Personalized Atrial Fibrillation Prediction on Multi-Core Wearable Sensors

David Atienza Alonso, Amir Aminifar, Miguel Peon Quiros, Adriana Arza Valdes, Elisabetta De Giovanni

In the recent Internet-of-Things (IoT) era where biomedical applications require continuous monitoring of relevant data, edge computing keeps gaining more and more importance. These new architectures for edge computing include multi-core and parallel compu ...

2020

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is an important part of database and MapReduce applications; however, it has not been studied as extensively as sorting of fixed-length keys. Handling variable-length keys in hardware is challenging and it is no surprise that no string sorte ...

IEEE COMPUTER SOC2020

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Babak Falsafi, Javier Picorel Obando, Abhishek Bhattacharjee

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TL ...

2020

Improved Masking for Tweakable Blockciphers with Applications to Authenticated Encryption

Robert Granger, Philipp Svetolik Jovanovic

A popular approach to tweakable blockcipher design is via masking, where a certain primitive (a blockcipher or a permutation) is preceded and followed by an easy-to-compute tweak-dependent mask. In this work, we revisit the principle of masking. We do so a ...

Springer Int Publishing Ag2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Caching Gaussians: Minimizing Total Correlation on the Gray–Wyner Network

Michael Christoph Gastpar, Guillaume Jean Op 't Veld

We study a caching problem that resembles a lossy Gray–Wyner network: A source produces vector samples from a Gaussian distribution, but the user is interested in the samples of only one component. The encoder first sends a cache message without any knowle ...

Ieee2016

Improved Masking for Tweakable Blockciphers with Applications to Authenticated Encryption

Robert Granger, Philipp Svetolik Jovanovic

2015

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Pentium

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function e(x)

Real-Time Personalized Atrial Fibrillation Prediction on Multi-Core Wearable Sensors

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Improved Masking for Tweakable Blockciphers with Applications to Authenticated Encryption

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Caching Gaussians: Minimizing Total Correlation on the Gray–Wyner Network

Hardware/Software Co-Design of Ultra-Low Power Biomedical Monitors

Improved Masking for Tweakable Blockciphers with Applications to Authenticated Encryption

Graph Chatbot

Chat with Graph Search

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function e(x)

Improved Masking for Tweakable Blockciphers with Applications to Authenticated Encryption

Real-Time Personalized Atrial Fibrillation Prediction on Multi-Core Wearable Sensors

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Caching Gaussians: Minimizing Total Correlation on the Gray–Wyner Network

Hardware/Software Co-Design of Ultra-Low Power Biomedical Monitors

Improved Masking for Tweakable Blockciphers with Applications to Authenticated Encryption