Concept

Single instruction, multiple data

Related publications (94)

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Optimal application-oriented resource brokering in a high performance computing grid

Vincent Keller

In the world of High Performance Computing (newly renamed "High Productivity Computing"), where the race for performance is on, where the hunt for the last Flop rages and where the developers swear by the Cult of Power, the different applications have diff ...

EPFL2008

Fast, quasi-optimal, and pipelined instruction-set extensions

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, the AFUs must satisfy certain constraints in terms of read and write ports betw ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

A new parallelized 3D SPH model: resolution of water entry problems ans scalability study

Pierre Maruzewski

The parallelized model is first presented and a scalability study is achieved. For computational time saving and memory requirement reasons, the implementation of a three dimensional SPH code implies the need for its parallelization, in order to make possi ...

2008

A simulator for adaptive parallel applications

Roger Hersch, Sebastian Gerlach

Dynamically allocating computing nodes to parallel applications is a promising technique for improving the utilization of cluster resources. Detailed simulations can help identify allocation strategies and problem decomposition parameters that increase the ...

2007

More Efficiency in Multiple Kernel Learning

An efficient and general multiple kernel learning (MKL) algorithm has been recently proposed by \singleemcite{sonnenburg_mkljmlr}. This approach has opened new perspectives since it makes the MKL approach tractable for large-scale problems, by iteratively ...

2007

More Efficiency in Multiple Kernel Learning

IDIAP2007

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Luca Benini

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple co ...

2006

Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Luca Benini

2006

Information Theoretic Combination of Classifiers With Application to Multiple SVMs

Jean-Philippe Thiran, Julien Meynet

Combining several classifiers has proved to be an efficient machine learning technique. Two concepts influence clearly the efficiency of an ensemble: the diversity between classifiers and the individual accuracies of the classifiers. We use an information ...

2006

Parallelization and scheduling of data intensive particle physics analysis jobs on clusters of PCs

Roger Hersch, Sébastien Ponce

Scheduling policies are proposed for parallelizing data intensive particle physics analysis applications on computer clusters. Particle physics analysis jobs require the analysis of tens of thousands of particle collision events, each event requiring typic ...

IEEE Computer Society, Los Alamitos;Massey University, Palmerston, CA 90720-1314, United States;New Zealand2004