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Related publications (39)

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Live demonstration: High level software and hardware synthesis of dataflow programs

Marco Mattavelli, Endri Bezati, Ghislain Roquier

This paper describes and demonstrates a toolchain which enables HW-SW co-synthesis from a single high-level dataflow program. This toolchain does not only enable rapid-prototyping of complex designs, but also provides a complete system integration framewor ...

2013

Reducing OLTP Instruction Misses With Thread Migration

Anastasia Ailamaki, Pinar Tözün

During an instruction miss a processor is unable to fetch instructions. The more frequent instruction misses are the less able a modern processor is to find useful work to do and thus performance suffers. Online transaction processing (OLTP) suffers from h ...

2012

Towards Static Analysis of Virtualization-Obfuscated Binaries

Johannes Kinder

Virtualization-obfuscation protects a program from manual or automated analysis by compiling it into bytecode for a randomized virtual architecture and attaching a corresponding interpreter. Static analysis appears to be helpless on such programs, where on ...

IEEE2012

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Christoph Studer

We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and ...

IEEE2010

Static Analysis of x86 Executables

Johannes Kinder

This dissertation is concerned with static analysis of binary executables in a theoretically well-founded, sound, yet practical way. The major challenge is the reconstruction of a correct control flow graph in presence of indirect jumps, pointer arithmetic ...

Technische Universität Darmstadt2010

Language Virtualization for Heterogeneous Parallel Computing

Martin Odersky, Tiark Rompf, Hassan Chafi

As heterogeneous parallel systems become dominant, application developers are being forced to turn to an incompatible mix of low level programming models (e.g. OpenMP, MPI, CUDA, OpenCL). However, these models do little to shield developers from the diffic ...

2010

P2P video broadcast with latency and utility optimization

Pascal Frossard

We consider the problem of mesh-pull based video broadcast in peer-to-peer networks. We propose a novel algorithm for constructing the distribution overlay, where peers are arranged in neighborhoods that exhibit similar latency values from the origin media ...

2009

Utility-based Packet Scheduling in P2P Mesh-based Multicast

Pascal Frossard

We consider streaming video content over an overlay network of peer nodes. We propose a novel streaming strategy that is built on utility-based packet scheduling and proportional resource sharing in order to fight against free- riders. Each of the peers em ...

2009

An Application-Specific Design Methodology for On-chip Crossbar Generation

Giovanni De Micheli, Luca Benini, Srinivasan Murali

Designing a power-efficient interconnection architec- ture for MultiProcessor Systems-on-Chips (MPSoCs) satisfying the application performance constraints is a nontrivial task. In order to meet the tight time-to-market constraints and to effec- tively hand ...

Institute of Electrical and Electronics Engineers2007

Dynamic feature selection for hardware prediction

Babak Falsafi

Most hardware predictors are table based (e.g. two-level branch predictors) and have exponential size growth in the number of input bits or features (e.g. previous branch outcomes). This growth severely limits the amount of predictive information that such ...

2006