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Atari 8-bit family

Related publications (9)

EdgeAI-Aware Design of In-Memory Computing Architectures

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Shashwat Shrivastava, Ognjen Glamocanin, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

Survey of Precision-Scalable Multiply-Accumulate Units for Neural-Network Processing

Christian Enz, Vincent Frédéric Camus

The current trend for deep learning has come with an enormous computational need for billions of Multiply-Accumulate (MAC) operations per inference. Fortunately, reduced precision has demonstrated large benefits with low impact on accuracy, paving the way ...

IEEE2019

Band Moire images

Roger Hersch, Sylvain Chosson

We propose a new powerful way of synthesizing moire images that enables the creation of dynamically moving messages incorporating text, symbols, and color elements. Moire images appear when superposing a base layer made of replicated base bands and a revea ...

2004

Efficient ASIC implementation of a real-time depth mapping stereo vision system

Andreas Peter Burg, Simon Karl Moser

This paper presents a fast and area-efficient implementation of a real-time stereo vision algorithm for spatial depth mapping. The design combines two well-known area-based approaches to stereo thatching and includes an occlusion detection method. Hardware ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2003

Near-optimal precharging in high-performance nanoscale CMOS caches

Babak Falsafi

High-performance caches statically pull up the bit-lines in all cache subarrays to optimize cache access latency. Unfortunately, such architecture results in a significant waste of energy in nanoscale CMOS implementations due to high leakage and bitline di ...

2003

An 8-bit low-power ADC array for CMOS image sensors

Steve Tanner, Michael Ansorge, Alexander Heubi

The paper presents an original analog-to-digital converter (ADC) array meeting the constraining requirements in resolution, speed, size, and low power consumption of high-performance low-cost video cameras. The converter array is based on ADC cells relying ...

1998

Absorption by dissociative continua and Rydberg states in condensed matter: HCl in rare gas matrixes

Majed Chergui

The absorption spectra of HCl in rare gas matrixes were recorded in the 1st continuum (A 1P->X 1S+) region in Kr and Xe matrixes and up to 100 nm in Ar matrixes. Concn. and temp. effects were used to distinguish between absorption from monomers and that fr ...

1996

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