Publications related to Thrashing (computer science)

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

David Atienza Alonso, Marina Zapater Sancho, Luis Maria Costero Valero, Darong Huang, Qunyou Liu

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use ...

2024

Benchmarking, Analysis, and Optimization of Serverless Function Snapshots

Edouard Bugnion, Evangelos Marios Kogias, Boris Robert Grot, Dmitrii Ustiugov

Serverless computing has seen rapid adoption due to its high scalability and flexible, pay-as-you-go billing model. In serverless, developers structure their services as a collection of functions, sporadically invoked by various events like clicks. High in ...

2021

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Robert Giterman

Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Rethinking Software Runtimes for Disaggregated Memory

Sanidhya Kashyap, Ivan Puddu

Disaggregated memory can address resource provisioning inefficiencies in current datacenters. Multiple software runtimes for disaggregated memory have been proposed in an attempt to make disaggregated memory practical. These systems rely on the virtual mem ...

ASSOC COMPUTING MACHINERY2021

Rebooting Virtual Memory with Midgard

Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yunho Oh, Abhishek Bhattacharjee

Computer systems designers are building cache hierarchies with higher capacity to capture the ever-increasing working sets of modern workloads. Cache hierarchies with higher capacity improve system performance but shift the performance bottleneck to addres ...

2021

Access pattern based optimization of memory access

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include identifying an access pattern associated with a database operation. The access pattern may include data required to perform the database operation. One or mor ...

2020

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Babak Falsafi, Javier Picorel Obando, Abhishek Bhattacharjee

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TL ...

2020

Exploiting Compute Caches for Memory Bound Vector Operations

Paolo Ienne, Gabriel Falcao Paiva Fernandes, João Miguel Morgado Pereira Vieira

To reduce the average memory access time, most current processors make use of a multilevel cache subsystem. However, despite the proven benefits of such cache structures in the resulting throughput, conventional operations such as copy, simple maps and red ...

IEEE2018

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Thrashing (computer science)

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

Benchmarking, Analysis, and Optimization of Serverless Function Snapshots

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Rethinking Software Runtimes for Disaggregated Memory

Rebooting Virtual Memory with Midgard

Access pattern based optimization of memory access

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Exploiting Compute Caches for Memory Bound Vector Operations

ADDICT: Advanced Instruction Chasing for Transactions

Graph Chatbot

Chat with Graph Search

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Benchmarking, Analysis, and Optimization of Serverless Function Snapshots

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Rebooting Virtual Memory with Midgard

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Access pattern based optimization of memory access

ADDICT: Advanced Instruction Chasing for Transactions

Exploiting Compute Caches for Memory Bound Vector Operations

Rethinking Software Runtimes for Disaggregated Memory