Publications related to Cache (computing)

Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yunho Oh, Abhishek Bhattacharjee

Computer systems designers are building cache hierarchies with higher capacity to capture the ever-increasing working sets of modern workloads. Cache hierarchies with higher capacity improve system performance but shift the performance bottleneck to addres ...

2021

Rethinking Software Runtimes for Disaggregated Memory

Sanidhya Kashyap, Ivan Puddu

Disaggregated memory can address resource provisioning inefficiencies in current datacenters. Multiple software runtimes for disaggregated memory have been proposed in an attempt to make disaggregated memory practical. These systems rely on the virtual mem ...

ASSOC COMPUTING MACHINERY2021

Efficient Streaming Subgraph Isomorphism with Graph Neural Networks

Karl Aberer, Quoc Viet Hung Nguyen, Chi Thang Duong, Trung-Dung Hoang

Queries to detect isomorphic subgraphs are important in graph-based data management. While the problem of subgraph isomorphism search has received considerable attention for the static setting of a single query, or a batch thereof, existing approaches do n ...

ASSOC COMPUTING MACHINERY2021

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Paolo Ienne, Mikhail Asiatici

Efficient large-scale graph processing is crucial to many disciplines. Yet, while graph algorithms naturally expose massive parallelism opportunities, their performance is limited by the memory system because of irregular memory accesses. State-of-the-art ...

IEEE COMPUTER SOC2021

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Robert Giterman

Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

Hybrid caches consisting of both SRAM and emerging Non-Volatile Random Access Memory (eNVRAM) bitcells increase cache capacity and reduce power consumption by taking advantage of eNVRAM's small area footprint and low leakage energy. However, they also inhe ...

2020

Caching (Bivariate) Gaussians

Michael Christoph Gastpar, Guillaume Jean Op 't Veld

Caching is a technique that alleviates networks during peak hours by transmitting partial information before a request for any is made. In a lossy setting of Gaussian databases, we study a single-user model in which good caching strategies minimize the dat ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Successive Refinement to Caching for Dynamic Requests

Michael Christoph Gastpar, Pinar Sen

In the celebrated coded caching problem studied by Maddah-Ali and Niesen, the peak-traffic network load is to be reduced by first caching some information about contents into individual memories of end users during the off-peak hours and then upon user req ...

IEEE2020

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Cache (computing)

Rebooting Virtual Memory with Midgard

Rethinking Software Runtimes for Disaggregated Memory

Efficient Streaming Subgraph Isomorphism with Graph Neural Networks

Software Support for Non-Volatile Memory (NVM) Programming

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Caching (Bivariate) Gaussians

Successive Refinement to Caching for Dynamic Requests

Graph Chatbot

Chat with Graph Search

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Software Support for Non-Volatile Memory (NVM) Programming

Efficient Streaming Subgraph Isomorphism with Graph Neural Networks

Rethinking Software Runtimes for Disaggregated Memory

Rebooting Virtual Memory with Midgard

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Caching (Bivariate) Gaussians

Successive Refinement to Caching for Dynamic Requests