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Stress has complex effects on memory function that can vary depending on the type of information that is learned and in relation to inter-individual characteristics. Recent work has also shown that stress can switch performance between memory systems, bias ...
The expansion of 3D real-time simulations (3DRTS) into millions of homes together with the technical progress of computers hardware force to approach software developments for 3DRTS from different perspectives. From an historical standpoint, 3DRTS started ...
Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...
Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...
Novel reconfigurable System-on-Chip (SoC) devices offer combining software with application-specific hardware accelerators to speed up applications. However, by mixing user software and user hardware, principal programming abstractions and system-software ...
This thesis introduces a new implementation of the LAIO api, liblaiogen. LAIO stands for Lazy Asynchronous I/O. It is an api for performing asynchronous I/O. Among several benefits, one of the most important is that LAIO is lazy, in the sense that it creat ...
In chip multiprocessors (CMPs), limiting the number of off-chip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlapp ...
Many instructional strategies that appear to improve learners' performance during training may not realize adequate posttest performance or transfer to a job. The converse has been found to be true as well: Instructional strategies that appear to slow the ...
Critical sections in database storage engines impact performance and scalability more as the number of hardware contexts per chip continues to grow exponentially. With enough threads in the system, some critical section will eventually become a bottleneck. ...
PROTOFLEX is an FPGA-accelerated hybrid simulation/emulation platform designed to support large-scale multiprocessor hardware and software research. Unlike prior attempts at FPGA multiprocessor system emulators, PROTOFLEX emulates full-system fidelity-i.e. ...
