Dominique de WerraDominique de Werra was born in Switzerland in 1942. He graduated in physical engineering at EPFL in 1965, and in 1969, a doctorate in technical sciences.
From 1969 to 1971 he was professor at Waterloo University (Canada) in the Management Sciences department. He has been a visiting professor in various European and American High Schools. In 1971 he became professor of Operations Research in Mathematics at EPFL. In 1990, he was appointed Vice President of EPFL and in addition, he became Director of training in autumn 1993.
His research focuses on discrete mathematics (combinatorial optimization, graph theory, algorithms, etc.) and their applications to industrial and informatics technology.
He has participated and directed several interdisciplinary projects in production, distribution, energy and scheduling. His work leads in particular to the time management problem and specifically to calendar management for important projects (sports, education, etc.).
In 1987-1988, he chaired the EURO association which encompasses the Operational Research in Europe. He is Dr. h.c. of Paris University and Ecole Polytechnique in Poznan, and he was the winner of the European gold medal (EURO) of Operational Research in 1995. In March 2000 he was appointed Dean of International Affairs.
Paolo IennePaolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.
