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Bluetooth stack

Related publications (16)

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An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

IEEE2022

Architecture Exploration and Optimization of Heterogeneous Many-Core Compute and Memory Architectures with Architectural Extensions

Yasir Mahmood Qureshi

The expeditious proliferation of Internet connectivity and the growing adoption of digital products have transformed various spheres of our everyday lives. This increased digitization of society has led to the emergence of new applications, which are deplo ...

EPFL2021

ANTIGONE: A Programmable Energy-Efficient Current Digitizer for an ISFET Wearable Sweat Sensing System

Maher Kayal, Evgenia Voulgari, François Krummenacher

This article describes the design and the characterization of the ANTIGONE (ANalog To dIGital cONvErter) ASIC (Application Specific Integrated Circuit) built in AMS 0.35 m technology for low dc-current sensing. This energy-efficient ASIC was specifically d ...

2021

Bluetooth (BR/EDR) and Bluetooth Low Energy (BLE) are pervasive wireless technologies specified in the Bluetooth standard. The standard includes key negotiation protocols used to generate long-term keys (during pairing) and session keys (during secure conn ...

ASSOC COMPUTING MACHINERY2020

A major theme of IT in the past decade has been the shift from on-premise hardware to cloud computing. Running a service in the public cloud is practical, because a large number of resources can be bought on-demand, but this shift comes with its own set of ...

EPFL2020

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The increasing ubiquity of edge devices in the consumer market, along with their ever more computationally expensive workloads, necessitate corresponding increases in computing power to support such workloads. In-memory computing is attractive in edge devi ...

2019

The IX Operating System: Combining Low Latency, High Throughput, and Efficiency in a Protected Dataplan

Edouard Bugnion, Christos Kozyrakis, Georgios Prekas, Mia Primorac, Ana Klimovic

The conventional wisdom is that aggressive networking requirements, such as high packet rates for small messages and μs-scale tail latency, are best addressed outside the kernel, in a user-level networking stack. We present ix, a dataplane operating system ...

Association for Computing Machinery2016

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The conventional wisdom is that aggressive networking requirements, such as high packet rates for small messages and microsecond-scale tail latency, are best addressed outside the kernel, in a user-level networking stack. We present IX, a dataplane operati ...

USENIX2014

A Bayesian Approach to Detect Pedestrian Destination-Sequences from WiFi Signatures

Michel Bierlaire, Bilal Farooq, Antonin Danalet

In recent years, interest in crowd dynamics and pedestrian modeling is reviving due to urban growth and its pressure on urban infrastructure. Crowd and pedestrian simulation is emerging as a tool for designing new infrastructures and optimizing the use of ...

2013

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs

Giovanni De Micheli, Federico Angiolini, Jaime Joven Murillo

Reconfigurable parallel computing is required to provide high-performance embedded computing, hide hardware complexity, boost software development, and manage multiple workloads when multiple applications are running simultaneously on the emerging network- ...

Institute of Electrical and Electronics Engineers2013