AMD APU | EPFL Graph Search

AMD Accelerated Processing Unit (APU), formerly known as Fusion, is a series of 64-bit microprocessors from Advanced Micro Devices (AMD), combining a general-purpose AMD64 central processing unit (CPU) and 3D integrated graphics processing unit (IGPU) on a single die. AMD announced the first generation APUs, Llano for high-performance and Brazos for low-power devices, in January 2011. The second generation Trinity for high-performance and Brazos-2 for low-power devices were announced in June 2012. The third generation Kaveri for high performance devices were launched in January 2014, while Kabini and Temash for low-power devices were announced in the summer of 2013. Since the launch of the Zen microarchitecture, Ryzen and Athlon APUs have released to the global market as Raven Ridge on the DDR4 platform, after Bristol Ridge a year prior. AMD has also supplied semi-custom APUs for consoles starting with the release of Sony PlayStation 4 and Microsoft Xbox One eighth generation video g

DSPE: Domain Specific Language for Parallel Real-Time Stream Processing

Tiziano Leidi

Today, the evolution of software solutions for parallel processing is strong, as a consequence of the mainstream introduction of chip-level multiprocessors. These types of parallel processors, which include general-purpose multi-cores and graphical processing units (GPUs), allow the execution of very intensive computations. However, depending on the nature of the executed applications, their effective exploitation may represent a complex task. In terms of parallel processing, the family of stream-processing applications is appealing because it features some forms of parallelism that may be exploited systematically. However, the processing performed by these types of applications is often real-time and, therefore, special-purpose support for parallel processing is required. The main contribution of this thesis is the DIGITAL STREAM-PROCESSING ENVIRONMENT (DSPE): an open-source development environment for rapid prototyping and customizing parallel real-time stream-processing applications. DSPE features a domain-specific language (DSL) based on model-driven generative programming that allows specifying applications at a high abstraction level. From the information provided with the DSL, generators are utilized to automatically produce the source code of applications. The source code generated by DSPE features dedicated infrastructures for parallel processing in stream-processing applications. These infrastructures are based on event-driven scheduling and on dynamic load balancing of lightweight tasks, which are techniques that limit the impact of load imbalances when parallel stream processing. Furthermore, DSPE supports the integration of kernels for GPUs for the exploitation of heterogeneous combinations of multi-core processors and GPUs. In DSPE, the generated source code can be configured to fit application- and hardware-specific needs. Furthermore, profile-guided, model-to-model transformations ease the migration from a serial version of an application to a parallel processing version. Experiments performed with DSPE on micro-benchmarks and sample applications demonstrate that the adopted approaches facilitate obtaining linear or near-to-linear scalings of the speed-up, when progressively incrementing the number of utilized processor cores.

EPFL2012

GPU-accelerated data management under the test of time

Anastasia Ailamaki, Angelos Christos Anadiotis, Periklis Chrysogelos, Syed Mohammad Aunn Raza, Panagiotis Sioulas

GPUs are becoming increasingly popular in large scale data center installations due to their strong, embarrassingly parallel, processing capabilities. Data management systems are riding the wave by using GPUs to accelerate query execution, mainly for analytical workloads. However, this acceleration comes at the price of a slow interconnect which imposes strong restrictions in bandwidth and latency when bringing data from the main memory to the GPU for processing. The related research in data management systems mostly relies on late materialization and data sharing to mitigate the overheads introduced by slow interconnects even in the standard CPU processing case. Finally, workload trends move beyond analytical to fresh data processing, typically referred to as Hybrid Transactional and Analytical Processing (HTAP). Therefore, we experience an evolution in three different axes: interconnect technology, GPU architecture, and workload characteristics. In this paper, we break the evolution of the technological landscape into steps and we study the applicability and performance of late materialization and data sharing in each one of them. We demonstrate that the standard PCIe interconnect substantially limits the performance of state-of-the-art GPUs and we propose a hybrid materialization approach which combines eager with lazy data transfers. Further, we show that the wide gap between GPU and PCIe throughput can be bridged through efficient data sharing techniques. Finally, we provide an H2TAP system design which removes software-level interference and we show that the interference in the memory bus is minimal, allowing data transfer optimizations as in OLAP workloads.

2020

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Aurélien François Gilbert Bloch, Simone Casale Brunet, Marco Mattavelli

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental components and features of both the design and of the platform to maximize the overall performance. The dataflow programming approach has proven to be an appropriate methodology for reaching such a difficult and complex goal for the intrinsic portability and the possibility of easily decomposing a network of actors on different processing units of the heterogeneous hardware. Nonetheless, such a design method might not be enough on its own to achieve the desired performance goals, and supporting tools are useful to be able to efficiently explore the design space so as to optimize the desired performance objectives. This article presents a methodology composed of several stages for enhancing the performance of dataflow software developed in RVC-CAL and generating low-level implementations to be executed on GPU/CPU heterogeneous hardware platforms. The stages are composed of a method for the efficient scheduling of parallel CUDA partitions, an optimization of the performance of the data transmission tasks across computing kernels, and the exploitation of dynamic programming for introducing SIMD-capable graphics processing unit systems. The methodology is validated on both the quantitative and qualitative side by means of dataflow software application examples running on platforms according to various different mapping configurations.

MDPI2022

DSPE: Domain Specific Language for Parallel Real-Time Stream Processing

Tiziano Leidi

EPFL2012