Skip to main content
Graph
Search
fr
|
en
Login
Search
All
Categories
Concepts
Courses
Lectures
MOOCs
People
Practice
Publications
Startups
Units
Show all results for
Home
Lecture
High-Level Synthesis: Formally Verified Elastic Circuits
Graph Chatbot
Related lectures (31)
Previous
Page 2 of 4
Next
Hoare Logic: Foundations and Applications
Covers Hoare Logic, its foundations, applications, and significance in program verification.
Lambda Calculus and Type Safety: An Overview
Provides an overview of lambda calculus, type safety, and type inference in programming languages.
Programmable Logic Devices: PAL, GAL, CPLD
Covers PAL, GAL, CPLD, and the transition to FPGAs using HDLs.
Quantum and Nanocomputing
Covers quantum and nanocomputing, focusing on molecules as conductive elements, molecular transistors, and field coupling elements.
Parallel Port & Nios II Interrupts
Covers the design of a programmable parallel port interface for an Avalon bus and the architecture of the Nios II processor.
An Introduction to Iris: Higher-Order Concurrent Separation Logic
Introduces Iris, a logical framework for reasoning about safety and correctness of concurrent higher-order imperative programs, emphasizing its unique characteristics and applications.
Generating a CLK Generator (PLL) IP in Vivado
Covers the process of generating a Clock Generator (PLL) IP in Vivado using the Clocking Wizard tool.
VHDL for Synthesis
Covers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.
Compiler verification: Challenges and Benefits
Explores the challenges and benefits of compiler verification, emphasizing the importance of verifying compilers for critical software.
Foundations of Software
Covers the basics of induction, syntax, abstract vs. concrete syntax, and operational semantics for Booleans.
