CS Stage: Small-Signal Model and Voltage Gain

In course

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Description

This lecture covers the small-signal model for the CS stage in IC design, including saturation and channel-length modulation effects. It also discusses the voltage gain in CS stages with resistive and diode-connected loads.

Instructor

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Official source

https://mediaspace.epfl.ch/media/0_dq33fusz

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Ontological neighbourhood

Physics

Electromagnetism: Electrical networks

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