Lectures related to NIOS II - Avalon Bus

Explores cache memory design, hits, misses, and eviction policies in computer systems, emphasizing spatial and temporal locality.

Explores the evolution and taxonomy of memories, focusing on SRAM and DRAM differences, memory layout, and functional taxonomy.

Covers direct-mapped and annex caches in computer architecture, explaining cache structure, access patterns, hit rates, and latency calculations.

Covers the design of a programmable parallel port interface for an Avalon bus and the architecture of the Nios II processor.

Focuses on implementing a square function generator using Speedgoat FPGA technology and real-time signal processing techniques.

Delves into RISC processor architecture, system design, microcontroller building blocks, and memory access.

Covers virtual memory, program relocation, memory protection, TLB, and memory hierarchy interactions.