Superscalars: Execution and Cache Requirements

In course

Aliquip consectetur nostrud non id id eu occaecat mollit. Veniam consequat incididunt culpa laborum esse. Labore irure ipsum ex ex ea dolor Lorem velit veniam quis exercitation labore. Fugiat tempor deserunt proident ad tempor ex mollit ad magna anim cillum. Excepteur do qui pariatur enim cillum esse aliquip. Labore nulla culpa Lorem veniam excepteur sint cupidatat sint minim aliqua esse cillum. Adipisicing nulla ea incididunt consequat incididunt excepteur ut mollit est.

Description

This lecture covers the concept of superscalar processors, focusing on executing multiple instructions per cycle and the cache requirements for optimal performance. It explains dynamic scheduling, nonblocking caches, dynamic branch prediction, and control speculation as key techniques to enhance Instruction Level Parallelism.

This video is available exclusively on Mediaspace for a restricted audience. Please log in to MediaSpace to access it if you have the necessary permissions.

Watch on Mediaspace

Official source

https://mediaspace.epfl.ch/media/0_lu0sjsvb

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Ontological neighbourhood

Computer engineering

Hardware engineering: Microprocessors

High-performance computing: Parallel computing

Related lectures (33)