Distributed Memory

This lecture covers the concept of distributed memory systems, focusing on topics such as cache organization, coherence, and consistency. It delves into the architecture of multi-socket systems, discussing the number of cores, bits for indexing directories, and block sizes. The instructor explains the challenges and solutions for memory coherence, emphasizing the importance of using the correct bus type. The lecture also explores the use of different bits for indexing directories and the implications for memory access within a socket. Additionally, it discusses the design considerations for on-chip interconnects, including routing and flow control mechanisms. The presentation concludes with an overview of RAMCloud, a storage system optimized for DRAM performance and scalability.