Lecture
This lecture covers the basic trade-offs in analog design, focusing on current optimization in a CS stage without VS, minimum bias current without VS, and the optimum bias current for achieving a given gain-bandwidth product. It discusses the impact of self-loading capacitance on bias current optimization and presents examples of CS stage sizing for a specific gain-bandwidth product. The lecture also delves into the concepts of inversion coefficient, bias current optimization, and the importance of current efficiency, transit frequency, and noise factor in low-power analog IC design.