Wladyslaw Grabinski

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Related publications (14)

A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction

Mihai Adrian Ionescu, Wladyslaw Grabinski, Arnab Biswas, Surya Shankar Dan

There are several techniques for junction profiling available in literature, yet none of them are practically suitable for the accurate determination of the lateral junction steepness in TFET devices, which is the most important parameter influencing TFET ...

Institute of Electrical and Electronics Engineers2012

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

Mihai Adrian Ionescu, Didier Bouvet, Wladyslaw Grabinski, Mohammad Najmzadeh

In this paper, we report for the first time making multi-gate buckled self-aligned dual Si nanowires including two sub-100 nm cross-section cores on bulk Si substrate using optical lithography, hard mask/spacer technology and local oxidation. 0.8 GPa uniax ...

Institute of Electrical and Electronics Engineers2012

TCAD Simulation of SOI TFETs and Calibration of Non-local Band-to-Band Tunneling Model

Mihai Adrian Ionescu, Wladyslaw Grabinski, Arnab Biswas, Surya Shankar Dan

This paper reports a simulation based study of the non-local tunneling model using a commercially available technology computer-aided design (TCAD) device simulator. Single gate Tunnel FET devices with 400nm gate length based on SOI technology are measured ...

Elsevier2012

Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

Mihai Adrian Ionescu, Jean-Michel Sallese, Didier Bouvet, Wladyslaw Grabinski, Mohammad Najmzadeh

In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5 ...

Elsevier2012

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