Publications by Seyed Armin Tajalli

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

In ultra-low-power (ULP) applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, re ...

Institute of Electrical and Electronics Engineers2011

Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

Seyed Armin Tajalli, Yusuf Leblebici

A sixth-order low-pass

g_m

-C filter with a very wide tuning range (

f_c

= 100 Hz to 10 MHz) is presented. The wide tuning range has been achieved without using switchable components or programmable building blocks. A single stage folded-cascode transcon ...

Institute of Electrical and Electronics Engineers2011

Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS

Seyed Armin Tajalli

The potentials of subthreshold metal-oxide-semiconductor (MOS) solid-state devices for implementing widely adjustable performance integrated circuits with very low power consumption have been investigated. The main concentration of this work is developing ...

EPFL2010

An area and power optimization technique for CMOS bandgap voltage references

Seyed Armin Tajalli, Mohammad Chahardori

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose ...

Springer US2010

Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits

Seyed Armin Tajalli, Yusuf Leblebici

This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed techniq ...

DATE2010

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Seyed Armin Tajalli, Yusuf Leblebici

A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three ...

2010

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

Seyed Armin Tajalli, Yusuf Leblebici

A current-mode

\Delta\Sigma

analog-to-digital data converter (ADC) for biomedical readout front-end systems is being presented. The core of this circuit is a current-controlled ring oscillator (CCO) whose oscillation frequency is proportional to the inpu ...

2010

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits

Seyed Armin Tajalli, Yusuf Leblebici

A very low power mixed-signal design methodology based on subthreshold source-coupled circuits is presented, and a nano-Watt range analog-to-digital converter (ADC) circuit based on folding-interpolating topology is proposed as a complete design example. T ...

2010

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold

Seyed Armin Tajalli, Yusuf Leblebici

A very wide tuning range ultra-low-power MOSFET-C filter is presented. The wide tuning range in this filter has been achieved without using any switchable components or programmable building blocks, and the cutoff frequency of the filter can be adjusted si ...

IEEE2009

A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology

Seyed Armin Tajalli, Yusuf Leblebici

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power p ...

2009

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Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS

An area and power optimization technique for CMOS bandgap voltage references

Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold

A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

An area and power optimization technique for CMOS bandgap voltage references

Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology

Nanowatt Range Folding-Interpolating ADC Using Subthreshold Source-Coupled Circuits