Publications by Fabio Sebastiano

Nano-MOSFET - Foundation of Quantum Computing Part I

As big strides were being made in many science fields in the 1970s and 80s, faster computation for solving problems in molecular biology, semiconductor technology, aeronautics, particle physics, etc., was at the forefront of research. Parallel and super-co ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

A 1-GS/s 6-8-b Cryo-CMOS SAR ADC for Quantum Computing

Edoardo Charbon, Fabio Sebastiano, Alessandro Catania

This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multipl ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

Edoardo Charbon, Fabio Sebastiano

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcor ...

IEEE2023

A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications

Edoardo Charbon, Fabio Sebastiano, Yue Chen

This article presents a 4-to-5 GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A Cryo-CMOS PLL for Quantum Computing Applications

Edoardo Charbon, Fabio Sebastiano

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit oper ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Cryogenic CMOS Circuits and Systems: Challenges and Opportunities in Designing the Electronic Interface for Quantum Processors

Edoardo Charbon, Fabio Sebastiano

Quantum computing could potentially offer faster solutions for some of today's classically intractable problems using quantum processors as computational support for quantum algorithms [1]. Quantum processors, in the most frequent embodiment, comprise an a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

A Low-Jitter and Low-Spur Charge-Sampling PLL

Edoardo Charbon, Fabio Sebastiano

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing an ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Fabio Sebastiano

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Nano-MOSFET - Foundation of Quantum Computing Part I

A 1-GS/s 6-8-b Cryo-CMOS SAR ADC for Quantum Computing

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications

A Cryo-CMOS PLL for Quantum Computing Applications

Cryogenic CMOS Circuits and Systems: Challenges and Opportunities in Designing the Electronic Interface for Quantum Processors

A Low-Jitter and Low-Spur Charge-Sampling PLL

A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS

A 6-to-8GHz 0.17mW/Qubit Cryo-CMOS Receiver for Multiple Spin Qubit Readout in 40nm CMOS Technology

A 2.7mW 45fS(rms)-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications

A Cryo-CMOS PLL for Quantum Computing Applications

Cryogenic CMOS Circuits and Systems: Challenges and Opportunities in Designing the Electronic Interface for Quantum Processors

A Low-Jitter and Low-Spur Charge-Sampling PLL

Nano-MOSFET - Foundation of Quantum Computing Part I

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications

A 1-GS/s 6-8-b Cryo-CMOS SAR ADC for Quantum Computing

A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS

A 6-to-8GHz 0.17mW/Qubit Cryo-CMOS Receiver for Multiple Spin Qubit Readout in 40nm CMOS Technology

A 2.7mW 45fS(rms)-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications