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Ciprian Seiculescu

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Ciprian Seiculescu

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Designing Best Effort Networks-on-Chip to Meet Hard Latency Constraints

3.5-D Integration: A Case Study

Design Methods and Tools for Application-Specific Predictable Networks-on-Chip

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

A DRAM Centric NoC Architecture and Topology Design Approach

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control