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Gain Kim

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A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links

Resistive random access memory based multiplexers and field programmable gate arrays

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme

Analysis, Optimization, and Modeling of Analog Multi-Tone Serial Data Transceivers

A Time-Division Multiplexing Signaling Scheme for Low-Power Multi-Drop Memory Links

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links