David Novo Bruna

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Related publications (16)

Design Space Exploration of LDPC Decoders Using High-Level Synthesis

Paolo Ienne, Nithin George, David Novo Bruna, Vitor Silva, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

2017

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures

Paolo Ienne, Grace Zgheib, David Novo Bruna, Manana Lortkipanidze

2016

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Andreas Peter Burg, Paolo Ienne, Georgios Karakonstantis, David Novo Bruna, Madhura Purnaprajna, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementatio ...

Assoc Computing Machinery2015

Automatic Application of Power Analysis Countermeasures

Paolo Ienne, Francesco Regazzoni, Ali Galip Bayrak, Philip Brisk, David Novo Bruna

We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channe ...

Institute of Electrical and Electronics Engineers2015

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash

Paolo Ienne, Xavier Jimenez, David Novo Bruna

Hybrid flash storages combine a small Single-Level Cell (SLC) partition with a large Multilevel Cell (MLC) partition. Compared to MLC-only solutions, the SLC partition exploits fast and short local write updates, while the MLC part brings large capacity. O ...

Assoc Computing Machinery2015

Majority-Inverter Graph for FPGA Synthesis

Giovanni De Micheli, Paolo Ienne, Ana Petkovska, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, David Novo Bruna

In this paper, we present an FPGA synthesis flow based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. MIG manipulation is supported by a consistent alge ...

2015

A technology mapper for depth-constrained FPGA logic cells

Paolo Ienne, Grace Zgheib, David Novo Bruna

2015

Automatic support for multi-module parallelism from computational patterns

Paolo Ienne, David Novo Bruna, Nithin George, David Loyd Andrews

2015

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis

Paolo Ienne, David Novo Bruna, Vitor Silva, Nithin George, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

2015

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Paolo Ienne, Barbara Jobstmann, David Novo Bruna, Andrew James Becker, Mohsen A A Ewaida

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meani ...

Springer2015

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From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis

Paolo Ienne, David Novo Bruna, Vitor Silva, Nithin George, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

2015

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Paolo Ienne, Barbara Jobstmann, David Novo Bruna, Andrew James Becker, Mohsen A A Ewaida

Springer2015