Publications by Camillo Stefanucci

SPICE Modeling of Photoelectric Effects in Silicon With Generalized Devices

Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella, Chiara Rossi

Modeling photoelectric effects in semiconductors with electrical simulators is demonstrated in typical 1-D and 2-D architectures. The concept is based on a coarse meshing of the semiconductor with the so-called generalized lumped devices, where equivalent ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Modeling Surface Recombination with Enhanced Devices Network for Optoelectronics

Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella, Chiara Rossi

We present a lumped devices network approach to simulate surface recombination effects in optoelectronics devices. The network is composed of generalized lumped devices where the excess carrier concentrations and gradients are mapped on electrical quantiti ...

IEEE2018

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult ...

Institute of Electrical and Electronics Engineers2016

Analysis of Substrate Currents Propagation in HVCMOS technology

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi ...

IEEE2016

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementar ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Active Guard Ring Characterization for Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This paper shows SPICE simulation results of active guard ring structures which are typically employed in Smart Power ICs. Active guard rings act as barriers limiting the flow of minority carriers injected into the substrate toward sensitive circuits. The ...

Ieee2016

Substrate modeling of parasitic couplings in Smart Power ICs with generalized lumped devices

Camillo Stefanucci

Today automotive industry is demanding more and more compact solutions for embedded electronics to be interfaced with vehicles components such as motor drivers, igniters and car communication buses. That is why Smart Power Integrated Circuits (IC) have bee ...

EPFL2016

Spice Simulation of Passive Protection in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electr ...

Ieee2015

Modeling Parasitic Vertical PNP in HVCMOS

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach ...

IEEE2015

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are prop ...

Institute of Electrical and Electronics Engineers2015