Publications by Giovanni Ansaloni

A Reconfigurable High-Dynamic Range ∆Σ Front-End with Event-Based Decimation for Bandwidth-Efficient Implantable Neural Interfaces

David Atienza Alonso, Giovanni Ansaloni, Pasquale Davide Schiavone, Juan Pablo Sapriza Araujo

As the demand for high channel counts and high-resolution recordings of neural activity continues to grow, the increased power and data rate generated impose hard constraints on the telemetry capabilities of wireless implantable neural interfaces. To addre ...

IEEE2025

HEEPstor: an Open-Hardware Co-design Framework for Quantized Machine Learning at the Edge

David Atienza Alonso, Giovanni Ansaloni, Rafael Medina Morillas

Edge-AI applications necessitate the joint application of hardware acceleration and software optimization to meet energy and area constraints. However, the co-design of these systems is hindered by the lack of integration options for novel hardware prototy ...

ACM2025

Keep All in Memory with Maxwell: a Near-SRAM Computing Architecture for Edge AI Applications

David Atienza Alonso, Giovanni Ansaloni, Grégoire Axel Eggermann

Recent advances in machine learning have dramatically increased model size and computational requirements, increasingly straining computing system capabilities. This tension is particularly acute for resource-constrained edge scenarios, for which careful h ...

IEEE2025

LIONHEART: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Irem Boybat Kara, Flavio Ponzina, Joshua Alexander Harrison Klein, Abu Sebastian

When arranged in a crossbar configuration, resistive memory devices can be used to execute Matrix-Vector Multiplications (MVMs), the most dominant operation of many Machine Learning (ML) algorithms, in constant time complexity. Nonetheless, when performing ...

Institute of Electrical and Electronics Engineers (IEEE)2025

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems

David Atienza Alonso, Giovanni Ansaloni, Rafael Medina Morillas

Efficient deployment of resource-intensive transformers on edge devices necessitates cross-stack optimization. We thus study the interrelation between structured pruning and systolic acceleration, matching the size of pruned blocks with the systolic array ...

Association for Computing Machinery2025

SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Rafael Medina Morillas, Pengbo Yu

By interfacing computing logic directly to the DRAM banks, bank-level Compute-near-Memory (CnM) architectures promise to mitigate the bottleneck at the memory interconnect. While this computation paradigm heavily reduces the energy requirements for data mo ...

ACM2025

Towards Accurate RISC-V Full System Simulation via Component-level Calibration

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Joshua Alexander Harrison Klein

Full-System (FS) simulation is essential for performance evaluation of complete systems that execute complex applications on a complete software stack consisting of an operating system and user applications. Nevertheless, they require careful fine-tuning a ...

Association for Computing Machinery (ACM)2025

A Reconfigurable High Dynamic Range Delta-Sigma Front End with Event-Based Decimation for Bandwidth-EfficientImplantable Neural Interfaces

David Atienza Alonso, Giovanni Ansaloni, Pasquale Davide Schiavone, Juan Pablo Sapriza Araujo

As the demand for high channel counts and high-resolution recordings of neural activity continues to grow, the increased power and data rate generated impose hard constraints on the telemetry capabilities of wireless implantable neural interfaces. To addre ...

2025

An MLIR-based Compilation Framework for CGRA Application Deployment

David Atienza Alonso, Giovanni Ansaloni, Lara Orlandic, Rubén Rodríguez Álvarez, Juan Pablo Sapriza Araujo

Coarse-Grained Reconfigurable Arrays (CGRAs) are a programmable architectural solution that efficiently supports the execution of computation-intensive application functions (kernels). Compilers for CGRAs typically focus on optimizing the mapping of single ...

2025

A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions

David Atienza Alonso, Giovanni Ansaloni, Juan Pablo Sapriza Araujo

At the intersection between traditional CPU architectures and more specialized options such as FPGAs or ASICs lies the family of reconfigurable hardware architectures, termed Coarse-Grained Reconfigurable Arrays (CGRAs). CGRAs are composed of a 2-dimension ...

ACM2025