Person

Andrea Bonetti

This person is no longer with EPFL

Related publications (22)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Andrea Bonetti

Graph Chatbot

Chat with Graph Search

ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories

Gain-Cell Embedded DRAMs: Modeling and Design Space

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories

Gain-Cell Embedded DRAMs: Modeling and Design Space

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Gain-Cell Embedded DRAMs: Modeling and Design Space

FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices