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Robert Giterman

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Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Lupulus: A Flexible Hardware Accelerator For Neural Networks

Gain-Cell Embedded DRAMs: Modeling and Design Space

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Gain-Cell Embedded DRAMs: Modeling and Design Space

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Lupulus: A Flexible Hardware Accelerator For Neural Networks