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Please note that this is not a complete list of this person’s publications. It includes only semantically relevant works. For a full list, please refer to Infoscience.
This article presents a design-for-test methodology for embedded memories. The methodology relies on a fully random fault model of post-fabrication errors, which results in a low-overhead test strategy. The methodology's effectiveness is demonstrated on an ...
A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomi ...
2022
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Communication systems have been associated with an inherent fault tolerance to hardware reliability issues. Therefore, many publications have studied the impact of such issues on, for example, channel (mostly LDPC) decoders. Since all of these studies are ...