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Stefan Nikolic

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Automating the Design of Programmable Interconnect for Reconfigurable Architectures

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

Turning PathFinder Upside -Down: 1-4,xploring FPGA Switch -Blocks by Negotiating Switch Presence

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Finding a Needle in the Haystack of Hardened Interconnect Patterns