Publications by Rafael Medina Morillas

HEEPstor: an Open-Hardware Co-design Framework for Quantized Machine Learning at the Edge

David Atienza Alonso, Giovanni Ansaloni, Rafael Medina Morillas

Edge-AI applications necessitate the joint application of hardware acceleration and software optimization to meet energy and area constraints. However, the co-design of these systems is hindered by the lack of integration options for novel hardware prototy ...

ACM2025

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems

David Atienza Alonso, Giovanni Ansaloni, Rafael Medina Morillas

Efficient deployment of resource-intensive transformers on edge devices necessitates cross-stack optimization. We thus study the interrelation between structured pruning and systolic acceleration, matching the size of pruned blocks with the systolic array ...

Association for Computing Machinery2025

SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Rafael Medina Morillas, Pengbo Yu

By interfacing computing logic directly to the DRAM banks, bank-level Compute-near-Memory (CnM) architectures promise to mitigate the bottleneck at the memory interconnect. While this computation paradigm heavily reduces the energy requirements for data mo ...

ACM2025

Bank on Compute-near-Memory: Design Space Exploration of Processing-near-Bank Architectures

Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas

Near-DRAM computing strategies advocate for providing computational capabilities close to where data is stored. Although this paradigm can effectively address the memoryto-processor communication bottleneck, it also presents new challenges: The strict reso ...

Institute of Electrical and Electronics Engineers (IEEE)2024

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Joshua Alexander Harrison Klein

Multi-Chiplet architectures are being increasingly adopted to support the design of very large systems in a single package, facilitating the integration of heterogeneous components and improving manufacturing yield. However, chiplet-based solutions have to ...

2023

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Darong Huang, Rafael Medina Morillas

2.5D Systems-on-Package (SoPs) are composed by several chiplets placed on an interposer. They are becoming increasingly popular as they enable easy integration of electronic components in the same package and high fabrication yields. Nevertheless, they int ...

2023

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

IEEE2022