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An Application-Specific Design Methodology for On-chip Crossbar Generation

Related publications (42)

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Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL.As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and s ...

EPFL2024

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators.Specialized hardware has already redefined ...

EPFL2023

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Marcos Vinícius Silva Oliveira

The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These ...

EPFL2021

FPGA Architecture: Principles and Progression

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Jonathan Emmanuel D Narinx

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

EPFL2019

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

Leading the Blind

Grace Zgheib

The design and development of innovative FPGA architectures hinge on the flexibility of its toolchain. Retargetable toolchains, like the Verilog-to-Routing (VTR) flow, have been developed to enable the testing of new FPGAs by mapping circuits onto easily-d ...

EPFL2017

Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems

Juan Sebastian Rodriguez Estupinan

In this thesis, the author proposes a circular system development model which considers all the stages in a typical development process for industrial systems. In particular, the present work shows that the use of virtual prototyping at early stages of the ...

EPFL2017

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

How to Measure the Killer Microsecond

Edouard Bugnion, Mia Primorac

Datacenter-networking research requires tools to both generate traffic and accurately measure latency and throughput. While hardware-based tools have long existed commercially, they are primarily used to validate ASICs and lack flexibility, e.g. to study n ...

Assoc Computing Machinery2017