Publications related to Reconfigurable Distributed Storage for Dynamic Networks

Planetary-Scale Byzantine Fault Tolerance

The scale and pervasiveness of the Internet make it a pillar of planetary communication, industry and economy, as well as a fundamental medium for public discourse and democratic engagement. In stark contrast with the Internet's decentralized infrastructur ...

EPFL2024

Secure Interface Design Leveraging Hardware/Software Support

Atri Bhattacharyya

Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

EPFL2024

Automated Formal Verification of Software Network Functions

Solal Vincenzo Pirelli

Formally verifying the correctness of software is necessary to merit the trust people put in software systems. Currently, formal verification requires human effort to prove that a piece of code matches its specification and code changes to improve verifiab ...

EPFL2024

Computational conceptual design — typological exploration of spatial truss systems through optimization

Corentin Jean Dominique Fivet, Pierluigi D'Acunto, Jonas Warmuth

Exploring a wide range of design options is crucial for every sound conceptual design process. In the conventional structural design workflow, optimization techniques are generally employed to generate well-performing design options. However, focusing only ...

International Association for Shell and Spatial Structures (IASS)2023

Byzantine Fault-Tolerance in Federated Local SGD Under 2f-Redundancy

Nirupam Gupta

In this article, we study the problem of Byzantine fault-tolerance in a federated optimization setting, where there is a group of agents communicating with a centralized coordinator. We allow up to

f

Byzantine-faulty agents, which may not follow a prescr ...

Piscataway2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators.Specialized hardware has already redefined ...

EPFL2023

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Finding cycles in directed graphs enables important applications in various domains such as finance, biology, chemistry, and network science. However, as the size of graph datasets continues to grow, it becomes increasingly difficult to discover cycles wit ...

arXiv2023

Not Yet Another Digital ID: Privacy-Preserving Humanitarian Aid Distribution

Carmela González Troncoso, Boya Wang, Wouter Lueks, Justinas Sukaitis

Humanitarian aid-distribution programs help bring physical goods to people in need. Traditional paper-based solutions to support aid distribution do not scale to large populations and are hard to secure. Existing digital solutions solve these issues, at th ...

IEEE COMPUTER SOC2023

Byzantine consensus is Θ(n^2): the Dolev-Reischuk bound is tight even in partial synchrony!

Rachid Guerraoui, Jovan Komatovic, Pierre Philippe Civit, Vincent Gramoli, Seth Gilbert, Manuel José Ribeiro Vidigueira

The Dolev-Reischuk bound says that any deterministic Byzantine consensus protocol has (at least) quadratic (in the number of processes) communication complexity in the worst case: given a system with n processes and at most f < n/3 failures, any solution t ...

2023

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, David Dervishi

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

Reconfigurable Distributed Storage for Dynamic Networks

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Planetary-Scale Byzantine Fault Tolerance

Secure Interface Design Leveraging Hardware/Software Support

Automated Formal Verification of Software Network Functions

Computational conceptual design — typological exploration of spatial truss systems through optimization

Byzantine Fault-Tolerance in Federated Local SGD Under 2f-Redundancy

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Not Yet Another Digital ID: Privacy-Preserving Humanitarian Aid Distribution

Byzantine consensus is Θ(n^2): the Dolev-Reischuk bound is tight even in partial synchrony!

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Secure Interface Design Leveraging Hardware/Software Support

Computational conceptual design — typological exploration of spatial truss systems through optimization

Planetary-Scale Byzantine Fault Tolerance

Automated Formal Verification of Software Network Functions

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Byzantine Fault-Tolerance in Federated Local SGD Under 2f-Redundancy

Byzantine consensus is Θ(n^2): the Dolev-Reischuk bound is tight even in partial synchrony!

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Not Yet Another Digital ID: Privacy-Preserving Humanitarian Aid Distribution