Publications related to Address partitioning in DSM clusters with parallel coherence controllers

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Access pattern based optimization of memory access

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include identifying an access pattern associated with a database operation. The access pattern may include data required to perform the database operation. One or mor ...

2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...

IEEE2020

Prefetched Address Translation

Edouard Bugnion, Boris Robert Grot, Dmitrii Ustiugov

With explosive growth in dataset sizes and increasing machine memory capacities, per-application memory footprints are commonly reaching into hundreds of GBs. Such huge datasets pressure the TLB, resulting in frequent misses that must be resolved through a ...

ASSOC COMPUTING MACHINERY2019

SoK: Shining Light on Shadow Stacks

Mathias Josef Payer, Xiangyu Zhang

Control-Flow Hijacking attacks are the dominant attack vector against C/C++ programs. Control-Flow Integrity (CFI) solutions mitigate these attacks on the forward edge, i.e., indirect calls through function pointers and virtual calls. Protecting the backwa ...

IEEE COMPUTER SOC2019

Pythia: Remote Oracles for the Masses

Mathias Josef Payer, Yuqing Zhang

Remote Direct Memory Access (RDMA) is a technology that allows direct access from the network to a machine's main memory without involving its CPU. RDMA offers low-latency, high-bandwidth performance and low CPU utilization. While RDMA provides massive per ...

USENIX ASSOC2019

SixTrack Version 5: Status and New Developments

Igor Zacharov, Riccardo De Maria, Giovanni Iadarola, Dario Pellegrini, Massimo Giovannozzi

SixTrack Version 5 is a major SixTrack release that introduces new features, with improved integration of the existing ones, and extensive code restructuring. New features include dynamic-memory management, scattering-routine integration, a new initial-con ...

IOP PUBLISHING LTD2019

A Novel Centralized Strategy for Coded Caching with Non-uniform Demands

Michael Christoph Gastpar, Pierre Victor Xavier Quinton, Saeid Sahraei

Despite significant progress in the caching literature concerning the worst case and uniform average case regimes, the algorithms for caching with nonuniform demands are still at a basic stage and mostly rely on simple grouping and memory-sharing technique ...

2018

Sky Monitoring System

Jean-Louis Scartezzini, Jérôme Henri Kämpf, Yujie Wu

In a sky monitoring system (S), comprising an image sensor (1), a wide angle lens (16), a microprocessor (3), and a memory unit (11, 18), wherein the sky monitoring system (S) is configured to take pictures of a sky scene, wherein the sky monitoring system ...

2018

Address partitioning in DSM clusters with parallel coherence controllers

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Access pattern based optimization of memory access

Distributed Computing with Modern Shared Memory

Gain-Cell Embedded DRAMs: Modeling and Design Space

Prefetched Address Translation

SoK: Shining Light on Shadow Stacks

Pythia: Remote Oracles for the Masses

SixTrack Version 5: Status and New Developments

Every data structure deserves lock-free memory reclamation

A Novel Centralized Strategy for Coded Caching with Non-uniform Demands

Sky Monitoring System

Access pattern based optimization of memory access

Distributed Computing with Modern Shared Memory

Pythia: Remote Oracles for the Masses

A Novel Centralized Strategy for Coded Caching with Non-uniform Demands

Every data structure deserves lock-free memory reclamation

SixTrack Version 5: Status and New Developments

SoK: Shining Light on Shadow Stacks

Prefetched Address Translation

Sky Monitoring System

Gain-Cell Embedded DRAMs: Modeling and Design Space