Publications related to Multiplex: Unifying conventional and speculative thread-level parallelism on a chip multiprocessor

Leveraging Hardware Message Passing for Efficient Thread Synchronization

André Schiper, Thomas Ropars, Darko Petrovic

As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ult ...

2014

Leveraging Hardware Message Passing for Efficient Thread Synchronization

André Schiper, Thomas Ropars, Darko Petrovic

Assoc Computing Machinery2014

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

Boris Robert Grot

As processor chips become increasingly parallel, an efficient communication substrate is critical for meeting performance and energy targets. In this work, we target the root cause of network energy consumption through techniques that reduce link and route ...

Institute of Electrical and Electronics Engineers2014

ATraPos: Adaptive Transaction Processing on Hardware Islands

Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Erietta Liarou

Nowadays, high-performance transaction processing applications increasingly run on multisocket multicore servers. Such architectures exhibit non-uniform memory access latency as well as non-uniform thread communication costs. Unfortunately, traditional sha ...

2014

Multi-Area Unit Scheduling and Reserve Allocation Under Wind Power Uncertainty

Ali Ahmadi Khatir, Antonio J. Conejo

This paper proposes a decentralized methodology to optimally schedule generating units while simultaneously determining the geographical allocation of the required reserve.We consider an interconnected multi-area power systemwith cross-border trading in th ...

Ieee-Inst Electrical Electronics Engineers Inc2014

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Sotiria Fytraki, Evangelos Vlachos

Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools. As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring. A recu ...

2014

Achieving high-throughput State Machine Replication in multi-core systems

André Schiper, Nuno Filipe de Sousa Santos

The traditional architecture used by implementations of Replicated State Machines (RSM) does not fully exploit modern multi-core CPUs. This is increasingly the limiting factor in their performance, because network speeds are increasing much faster than the ...

Ieee2013

Task Scheduling for Highly Concurrent Analytical and Transactional Main-Memory Workloads

Anastasia Ailamaki, Iraklis Psaroudakis

Task scheduling typically employs a worker thread per hardware context to process a dynamically changing set of tasks. It is an appealing solution to exploit modern multi-core processors, as it eases parallelization and avoids unnecessary context switches ...

2013

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Multiplex: Unifying conventional and speculative thread-level parallelism on a chip multiprocessor

Leveraging Hardware Message Passing for Efficient Thread Synchronization

Leveraging Hardware Message Passing for Efficient Thread Synchronization

High-Performance Communication Primitives and Data Structures on Message-Passing Manycores

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

ATraPos: Adaptive Transaction Processing on Hardware Islands

Multi-Area Unit Scheduling and Reserve Allocation Under Wind Power Uncertainty

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

Achieving high-throughput State Machine Replication in multi-core systems

Task Scheduling for Highly Concurrent Analytical and Transactional Main-Memory Workloads

Graph Chatbot

Chat with Graph Search

Leveraging Hardware Message Passing for Efficient Thread Synchronization

High-Performance Communication Primitives and Data Structures on Message-Passing Manycores

ATraPos: Adaptive Transaction Processing on Hardware Islands

Leveraging Hardware Message Passing for Efficient Thread Synchronization

Task Scheduling for Highly Concurrent Analytical and Transactional Main-Memory Workloads

Multi-Area Unit Scheduling and Reserve Allocation Under Wind Power Uncertainty

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

Achieving high-throughput State Machine Replication in multi-core systems

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring