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Multiplex: Unifying conventional and speculative thread-level parallelism on a chip multiprocessor

Related publications (135)

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Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip

David Atienza Alonso

Technology scaling imposes an ever increasing temperature stress on digital circuit design due to transistor density, especially on highly integrated systems, such as Multi- Processor Systems-on-Chip (MPSoCs). Therefore, temperature-aware design is mandato ...

IEEE Computer Society2009

ReSim, a Trace-Driven, Reconfigurable ILP Processor Simulator

Dionysios Pnevmatikatos, Sotiria Fytraki

Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration relies on extensive use of software simulation that when highly accurate is slow. ...

2009

Shore-MT: A Scalable Storage Manager for the Multicore Era

Anastasia Ailamaki, Babak Falsafi, Frederick Ryan Johnson, Ippokratis Pandis

Database storage managers have long been able to efficiently handle multiple concurrent requests. Until recently, however, a computer contained only a few single-core CPUs, and therefore only a few transactions could simultaneously access the storage manag ...

ACM2009

Stretching Transactional Memory

Rachid Guerraoui, Michal Kapalka, Aleksandar Dragojevic

Transactional memory (TM) is an appealing abstraction for programming multi-core systems. Potential target applications for TM, such as business software and video games, are likely to involve complex data structures and large transactions, requiring speci ...

2009

Why STM can be more than a Research Toy

Rachid Guerraoui, Vincent Gramoli, Aleksandar Dragojevic, Pascal Felber

Software Transactional Memory (STM) promises to simplify concurrent programming without requiring speciﬁc hardware support. Yet, STM’s credibility lies on the extent to which it can leverage multi-cores to outperform sequential code. A recent CACM paper [8 ...

2009

Temporal streams in commercial server applications

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

Commercial server applications remain memory bound on modern multiprocessor systems because of their large data footprints, frequent sharing, complex non-strided access patterns, and long chains of dependant misses. To improve memory system performance des ...

2008

Stall Power Reduction in Pipelined Architecture Processors

Pejman Lotfi Kamran

This paper proposes a technique for dynamic power reduction of pipelined processors. Pipelined processors frequently insert NOP instruction to the pipe for generating delay or resolving dependency. Our study shows that the percentage of power consumed by N ...

2008

Stretching Transactional Memory

Rachid Guerraoui, Michal Kapalka, Aleksandar Dragojevic

2008

Scheduling threads for constructive cache sharing on CMPs

Anastasia Ailamaki, Babak Falsafi

In chip multiprocessors (CMPs), limiting the number of offchip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlappi ...

2007

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches

Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same application, may require a different capacity-speed tradeo ...

2007