Publication

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Related publications (84)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Graph Chatbot

Chat with Graph Search

Network-on-chip using request and reply trees for low-latency processor-memory communication

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

FinFET integrated low-power circuits for enhanced sensing applications

Die-Stacked DRAM Caches for Servers: Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache

A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA

Beyond Scaling

SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads

RF Compact Modeling of High-voltage MOSFETs

Process Variation and Leakage Power