Publication

Last-touch correlated data streaming

Related publications (39)

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Efficient resource sharing in concurrent error detecting superscalar microarchitectures

Babak Falsafi

Previous proposals for soft-error tolerance have called for redundantly executing a program as two concurrent threads on a superscalar microarchitecture. In a balanced superscalar design, the extra workload from redundant execution induces a severe perform ...

2004

Using Cohort-Scheduling to Enhance Server Performance

James Richard Larus

A server application is commonly organized as a collection of concurrent threads, each of which executes the code necessary to process a request. This software architecture, which causes frequent control transfers between unrelated pieces of code, decrease ...

Usenix2002

Dead-block prediction & dead-block correlating prefetchers

Babak Falsafi

Effective data prefetching requires accurate mechanisms to predict both “which” cache blocks to prefetch and “when” to prefetch them. This paper proposes the Dead-Block Predictors (DBPs), trace-based predictors that accurately identify “when” an Ll data ca ...

2001

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Babak Falsafi

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately, reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold ...

2001

Reducing leakage in a high-performance deep-submicron instruction cache

Babak Falsafi

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold ...

2001

Gated-Vdd: a circuit technique to reduce leakage in deep- submicron cache memories

Babak Falsafi

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applica ...

2000

Spyder

Christian Iseli

The Spyder project consists of the development of a reconfigurable processor as well as its application development environment. The name Spyder is an anagram of the first letters of "REconfigurable Processor Development SYstem", where the term reconfigura ...

EPFL1996

Mechanisms for Cooperative Shared Memory

Babak Falsafi, James Richard Larus, David Wood

We introduce a new organization for multi-bank caches: the skewed-associative cache. A two-way skewed-associative cache has the same hardware complexity as a two-way set-associative cache, yet simulations show that it typically exhibits the same hit ratio ...

1994

Compiling for Shared-Memory and Message-Passing Computers

James Richard Larus

ACM1993