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Concerns over rising soft-error rates in processor logic has led to numerous proposals for error tolerance mechanisms. In this paper, we examine the role of soft-error containment in a shared memory multiprocessor. We study a range of design alternatives based on how far outside the processor core errors are allowed to propagate. We discuss tradeoffs in recovery complexity and error-free performance that arise from the choice of containment granularity.
André Schiper, Thomas Ropars, Darko Petrovic
Baptiste Joseph Eustache Lepers
Baptiste Joseph Eustache Lepers