Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
The aim of this research is to develop and to evaluate devices and circuits performances based on ultrathin nanograin polysilicon wire (polySiNW) dedicated to room temperature operated hybrid CMOS-"nano" integrated circuits. The proposed polySiNW device is ...
Today's world of electronics becomes more and more digital and therefore CMOS becomes the dominant technology. A CMOS process compared to a bipolar process offers several advantages, mainly a low power consumption which is important for portable systems po ...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have focused on adaptive post-fabrication tuning approaches to mitigate this prob ...
This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate cont ...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have focused on adaptive post-fabrication tuning approaches to mitigate this prob ...
Standard static CMOS logic is responding to the requirement of high frequency and low power of digital systems. However, the digital switching noise generated by this logic is not suited for the design of performance mixed-signal integrated systems. In mix ...
An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is based on the depletion approximation and expresses the pull-in voltage, the pull-out voltage, and t ...
The quickening pace of the MOSFET technology scaling has pushed the MOSFET dimension towards 10 nanometer channel length, where it is going to face the following fundamental and performance limiting factors: (i) electrostatic limits, (ii) source to drain t ...
As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output ( ...
