Software Code Generation for the RVC-CAL Language

Ghislain Roquier
2009
Journal paper

Abstract

The MPEG Reconﬁgurable Video Coding (RVC) framework is a new standard under development by MPEG that aims at providing a uniﬁed high-level speciﬁcation of current and future MPEG video coding technologies using dataﬂow models. In this framework, a decoder is built as a conﬁguration of video coding modules taken from the standard MPEG toolbox library or proprietary libraries. The elements of the library are speciﬁed by a textual description that expresses the I/O behavior of each module and by a reference software written using a subset of the CAL Actor Language named RVC-CAL. A decoder conﬁguration is written in an XML dialect by connecting a set of CAL modules. Code generators are fundamental supports that enable the direct transformation of a high level speciﬁcation to efﬁcient hardware and software implementations. This paper presents a synthesis tool that from a CAL dataﬂow program generates C code is validated against the original CAL description simulated using the Open Dataﬂow environment. Experimental results of the translation of two descriptions of an MPEG-4 Simple Proﬁle decoder with different granularities are shown and discussed.

Official source

https://infoscience.epfl.ch/record/143592?ln=en

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The growing complexity of signal processing algorithms and platforms poses significant challenges to design methods and implementation tools. High-level dataflow programs, such as those in MPEG's RVC-CAL language, provide abstraction and the opportunity for extensive design-space exploration, but they do raise the problem of efficient automatic synthesis to hardware and software. This paper presents a tool called Xronos that efficiently synthesizes RVC-CAL programs to an RTL-level hardware description and significantly improves on previous efforts in both quality of the resulting implementation and synthesis speed. By directly supporting all the features of the RVC-CAL language, it translates unmodified standard MPEG reference code to a functioning hardware implementation. The paper describes the essential processing architecture of Xronos, the differences from other related approaches and experimental results that show Xronos to produce faster and smaller implementations, while at the same time significantly reducing synthesis times.

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2008

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The possibility of specifying both SW and HW components using the same language is a very attractive design approach. However, despite the efforts spent for implementing such approach using common programming languages such as C and C++, it has not yet shown to be viable and efficient for complex design. The main reason is the difficulty of expressing architectural properties at the level of a common description, difficulty that finally results into the failure of synthesizing efficient HW and efficient parallel SW. This is not the case for dataflow programming that is well- suited to the description of complex real-world computational systems that may contain appreciable amounts of concurrency. A CAL [1, 2] dataflow program is a collection of actors connected by lossless first-in/first-out (FIFO) communication channels, through which they exchange packets of data called tokens. Each actor executes in a sequence of steps, during which it can (1) consume input tokens, (2) produce output tokens, (3) modify its own local state. Actors strictly encapsulate their state, i.e. they cannot directly use or modify the state of other actors. Consequently, executing actors concurrently does not cause race conditions on any state variables, which makes dataflow an excellent (and scalable) parallel programming model. This in turn is key to the generation of efficient HW and SW implementations. This demonstration presents an integrated environment that embeds the synthesis tool that translates a CAL-based dataflow specification into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed by a processor and a FPGA platform just by annotating the CAL specification. The possibility of direct synthesis from a high level specification is a crucial issue for enabling efficient re-design cycles that include rapid prototyping and validation of performances of the final implementation. The design approach enabled by such integrated environment is particularly suited for development of complex processing systems such as video codecs. As a case study, the demonstration provides the analysis and validation of different SW and HW partitioning of a MPEG-4 Simple Profile decoder.

IEEE2009

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IEEE2009