A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control
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In this paper we present the manner the POEtic chip can be used to rapidly prototype systems. This chip, currently in test phase, is a system-on-chip containing a microprocessor and a reconfigurable array. Spe- cial features allow to dynamically create dat ...
Networks-on-chip provide an elegant framework to efficiently reuse predesigned cores. However, reuse of cores is jeopardized by new deep sub-micron noise effects that challenge the reliability of CMOS technology. Moreover, noise margins are further reduced ...
We present a framework for the incremental construction of deadlock-free systems meeting given safety properties. The framework borrows concepts and basic results from the controller synthesis paradigm by considering a step in the construction process as a ...
The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of network-on-chip (NoC) ar ...
Institute of Electrical and Electronics Engineers2005