A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems
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This abstract presents a perform study on SOLERO, a new and innovative rover concept for regional mobility on planetary surfaces. A rover is the most suited element to bring scientific instrument to a specific site in order to examine geology, mineralogy o ...
Multiple clock domains is one solution to the increasing problem of propagating the clock signal across increasingly larger and faster chips. The ability to independently scale frequency and voltage in each domain creates a powerful means of reducing power ...
This thesis aims at developing wireless systems with a strong emphasis on low-power consumption and low-voltage operation. The main technical objective is the development of a single cells battery operated fully integrated CMOS RF transceiver that fulfills ...
To provide a scalable communication infrastructure for Systems on Chips (SoCs), Networks on Chips (NoCs), a communication centric design paradigm is needed. To be cost effective, SoCs are often programmable and integrate several different applications or u ...
This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with i ...
This paper presents a continuous voltage and frequency scaling approach achieving lower transition (both energy and time) overheads implied by changing voltage levels, at a very low power dissipation and silicon area cost for multi-processor systems with i ...
This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying ...
Portable systems require long battery lifetime while still delivering high performance. Dynamic power management (DPM) policies trade off the performance for the power consumption at the system level in portable devices. In this work we present the time-in ...
Dynamic power management is a design methodology aiming at controlling performance and power levels of digital circuits and systems, with the goal of extending the autonomous operation time of battery-powered systems, providing graceful performance degrada ...