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In this work, MOS Current Mode Logic (MCML) is analyzed for low power, low noise, mixed signal applications demanding high security such as embedded cryptographic processors and smart cards. We emphasize the possible extension of MCML gate usage for low sp ...
This paper presents a new two-sections architecture of a low power switched capacitor (SC) finite impulse response (FIR) filter suitable for base-band signal processing in WCDMA and in GSM standards. The low power operation is possible due to several optim ...
A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility. Their design highligh ...
This thesis aims at developing wireless systems with a strong emphasis on low-power consumption and low-voltage operation. The main technical objective is the development of a single cells battery operated fully integrated CMOS RF transceiver that fulfills ...
This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) in an SCL gate by a factor close to two. The proposed approach ha ...
This paper presents a solar charger ASIC for Nickelbased (NiCd or NiMH) batteries. The system is fully integrated and no external component is needed. The ASIC includes a voltage reference, a low-impedance switch, an oscillator, a poweron reset, and a digi ...
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Power Factor Corrected rectifiers are a new tendency in development of power supplies. In the last few years, a lot of R&D activities have led to a new category of products for one-phase applications. In this contribution, a new simplified topology is prop ...
In this paper, we study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages.We show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly ...
This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power p ...
This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate cont ...