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High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

Related publications (48)

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High-Performance Modular Multiplication on the Cell Processor

Joppe Willem Bos

This paper presents software implementation speed records for modular multiplication arithmetic on the synergistic processing elements of the Cell broadband engine (Cell) architecture. The focus is on moduli which are of special interest in elliptic curve ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

High-Performance Modular Multiplication on the Cell Processor

Joppe Willem Bos

Springer Berlin Heidelberg2010

ECC2K-130 on Cell CPUs

Joppe Willem Bos, Thorsten Kleinjung

This paper describes an implementation of Pollard's rho algorithm to compute the elliptic curve discrete logarithm for the Synergistic Processor Elements of the Cell Broadband Engine Architecture. Our implementation targets the elliptic curve discrete loga ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Montgomery Multiplication on the Cell

Joppe Willem Bos, Marcelo Kaihara

A technique to speed up Montgomery multiplication targeted at the Synergistic Processor Elements (SPE) of the Cell Broadband Engine is proposed. The technique consists of splitting a number into four consecutive parts. These parts are placed one by one in ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Through Silicon Via-Based Grid for Thermal Control in 3D Chips

David Atienza Alonso, Yusuf Leblebici, Arvind Raj Mahankali Sridhar, José Luis Ayala Rodrigo, Vinod Pangracious

3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between processing cores, and an effective way to diminish this impact on communica ...

Springer2009

Method to manage the load of peripheral elements within a multicore system

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini

The aim of the present invention is to propose a method to provide reliability, power management and load balancing support for multicore systems based on Networks- on-Chip (NoCs) as well as a way to efficiently implement architectural support for this met ...

2008

Deep-submicron embedded processor architectures for high-performance, low-cost and low-power

Sylvain Aguirre

Because the market has an insatiable appetite for new functionality, performance is becoming an increasingly important factor. The telecommunication and network domains are especially touched by this phenomenon but they are not the only ones. For instance, ...

EPFL2007

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

Eric Vittoz, Yusuf Leblebici, Zeynep Toprak Deniz

This work presents the design and the silicon implementation of an on-line energy optimizer unit based on novel analog computation approaches, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing ...

2007

Adding limited reconfigurability to superscalar processors

Marc Epalza

For the last thirty years, electronics, at first built with discrete components, and then as Integrated Circuits (IC), have brought diverse and lasting improvements to our quality of life. Examples might include digital calculators, automotive and airplane ...

EPFL2004

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

Nowaday, the world of processors is still dominated by the RISC architectures, which foundations have been laid down in the 70's. The RISC concept may be summarized by one word : simplicity. With this concept, much simpler architectures are born, in partic ...

EPFL2004